| 摘要 |
A method of fabricating an EEPROM includes the steps of sequentially forming a gate oxide layer, first polysilicon layer, first insulating layer, second polysilicon layer and insulating layer on a semiconductor substrate, etching the insulating layer and second polysilicon layer using a mask to form a gate mother pattern for forming a gate pattern, forming a second insulating layer on the overall surface of the substrate, etching back th second insulating layer to form a sidewall insulating layer on the sides of the gate mother pattern and exposing the first polysilicon layer, forming a third polysilicon layer on the overall surface of the substrate, dry-etching the third polysilicon layer to expose the top of the gate mother pattern, thereby forming a polysilicon sidewall connected to the sidewall insulating layer of the gate mother pattern and the first polysilicon layer, and performing ion implantation using the gate electrode to form source and drain regions in predetermined portions of the substrate.
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