Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed

摘要

In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associated with the respective semiconductor memory modules, and a timing varying unit for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.