| 摘要 |
Disclosed is a process for fabricating capacitor cells in DRAM chips allowing the capacitor cells thus fabricated to have higher capacitance by providing a stacked fin-like structure. The process comprises the following steps of: (1) forming on a substrate a field oxide layer, transistor cell, and insulation layer having a contact opening; (2) forming a stacked structure consisting of a plurality of alternately formed first polysilicon layers and insulation spacers; (3) forming an opening through the first polysilicon layers and insulation spacers in the stacked structure by etching; (4) etching away portions of the first polysilicon layers that are exposed on the inner wall of the opening so as to form a plurality of grooves in the opening; (5) forming a second polysilicon layer to the inner wall of the opening so as to cover the grooves; (6) defining a range for the capacitor cell by etching the second polysilicon layer and the first polysilicon layers and insulation spacers in the stacked structure, whereby part of the second polysilicon layer that is connected to each of the first polysilicon layers in the stacked structure serves as a bottom plate for the capacitor cell; (7) removing each of the insulation spacers in the stacked structure whiling retaining the bottom plate; (8) forming a dielectric layer covering the bottom plate; and (9) forming a third polysilicon layer covering the dielectric layer to serve as a top plate for the capacitor cell.
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