| 摘要 |
Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The PRBS generator may generate 1 and -1 randomly and the subsequent accumulator may accumulate the random signal. The lowpass filter may be used to eliminate the high frequency spur and the quantization noise. The gain controller may control an amount of the accumulated jitter. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller. A size of the counter may be proportional to the maximum period of the sinusoid jitter and the frequency of the sinusoid jitter may be controlled by selecting a speed of the counter. The counter number may select a value of the jitter from the sinusoid jitter profile lookup table, and the gain controller may control the amplitude of the jitter. |
