发明名称 |
Four device SRAM cell with single bitline |
摘要 |
A memory cell includes a static inverter having an input connected to a storage node. An impedance connects the storage node to a voltage supply. A first transistor, having an input connected to an output of the static inverter, connects the storage node to a write line. Lastly, a second transistor, responsive to a wordline access signal, connects the storage node to a single data bitline. The memory cell further includes a single ended four transistor CMOS SRAM cell. Additionally, a memory array is disclosed which includes a plurality of memory cells arranged to form a matrix of rows and columns, each memory cell including a single ended four transistor CMOS SRAM cell.
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申请公布号 |
US5805496(A) |
申请公布日期 |
1998.09.08 |
申请号 |
US19960773561 |
申请日期 |
1996.12.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BATSON, KEVIN ARTHUR;ROSS, JR., ROBERT ANTHONY |
分类号 |
G11C11/41;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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