Address bus arbiter for pipelined transactions on a split bus

摘要

An address bus arbiter is implemented using a state machine. A first through third states of the state machine grant the address bus to a respective first through third bus masters, each having a different priority associated therewith. Idle states are interposed between states. The idle state may be reached from one the bus grant states when a cache controller initiates a tag invalidation cycle or a cache allocation cycle. The idle state may also be reached when a first bus master commences a transaction cycle with a second bus master.