PASSIVIERUNG MIT HOHER LEISTUNG FUER HALBLEITERANORDNUNGEN

摘要

PCT No. PCT/CA92/00346 Sec. 371 Date Feb. 23, 1994 Sec. 102(e) Date Feb. 23, 1994 PCT Filed Aug. 10, 1992 PCT Pub. No. WO93/04501 PCT Pub. Date Mar. 4, 1993A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.