Microprocessor architecture capable of supporting multiple heterogenous processors

摘要

A multiprocessor system, comprising a plurality of microprocessors; and a memory array unit (MAU); wherein each of said microprocessors comprises master devices and slave devices, said slave devices including a memory port coupled to said MAU, and a memory control unit (MCU) for controlling access to said memory port; wherein said MCU comprises: a switch network for transferring data between said master devices and said memory port; a memory port interface circuit; means for coupling said memory port interface circuit between said memory port and said switch network; switch arbitration means for arbitrating for said switch network; port arbitration means for arbitrating for said memory port; means for transferring to said port arbitration means a request to transfer data via said memory port through said switch network and said port interface circuit; means for transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request; and means responsive to said port available signal for transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means which said switch network is free to process said request.