发明名称 |
Packing density for flash memories |
摘要 |
Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
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申请公布号 |
US5892257(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19960708432 |
申请日期 |
1996.09.05 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ACOCELLA, JOYCE ELIZABETH;GALLI, CAROL;HSU, LOUIS LU-CHEN;OGURA, SEIKI;ROVEDO, NIVO;SHEPARD, JOSEPH FRANCIS |
分类号 |
H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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