发明名称 3D-Verbindungsverfahren für Gehäuse von elektronischen Bauteilen und resultierendes 3D-Bauteil
摘要 The subject of the present invention is the interconnection of stacked housings, each of the housings, for example, encapsulating a semiconductor chip containing an integrated circuit, a memory for example. To this end, housings (2) equipped with connecting pins (21) and mounted on a support grid (4) preferably forming a thermal sink, are stacked and secured to one another with the aid of a resin coating (5), for example. The stacking is cut up in such a way that the pins of the housings and the grid come flush with the faces (31, 32) of the stacking (3). The connection of the housings together and of the latter to connecting terminals of the stack is carried out on the faces of the stack. The connecting terminals are, as appropriate, equipped with connecting pins. <IMAGE>
申请公布号 DE69322477(T2) 申请公布日期 1999.04.29
申请号 DE1993622477T 申请日期 1993.10.01
申请人 THOMSON-CSF, PARIS, FR 发明人 VAL CHRISTIAN, VAL CHRISTIAN, F-92402 COURBEVOIE CEDEX, FR
分类号 H01L23/52;H01L25/00;H01L25/065;H01L25/10;H01L25/11;H01L25/18;(IPC1-7):H01L25/10 主分类号 H01L23/52
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