| 摘要 |
A flexible architecture for a digital data receiver including a demultiplexer is provided which allows modular addition of data processors with low complexity and minimal memory requirements. The demultiplexer operates on a scalable frame-based multiplex signal, and interprets the multiplex control data at the start of the frame. With the information interpreted from the control data, the demultiplexer separates individual data services and optionally decrypts them. Data, a data clock and an error flag signal are presented to the demultiplexer input. According to a service requested by a user, the demultiplexer outputs decrypted data clock, error flag and service enable signals in a flow-through manner to an appropriate data processor without data storage.
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