| 摘要 |
A floating point addition and subtraction circuit includes a comparison subtraction circuit receiving two operands to be processed for making a comparison in the size between their exponent parts so as to subtract the smaller exponent part from the larger one, the comparison subtraction circuit providing the comparison result and the subtraction result. A mantissa selecting circuit and a shift circuit align the mantissa of the operand. Leading zero counting circuit counts the number of zeros successively positioned in the high order direction from the least significant bit of the mantissa of the operand having the smaller operand. Comparator circuit compares the counting result and the subtraction result by the comparison subtraction circuit, to thereby detect a sticky bit according to the comparison result. An absolute value addition and subtraction arithmetic circuit receives the aligned mantissas of the two operands and the detected sticky bit, and performs an addition or subtraction operation on the operands.
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