发明名称 |
Branch instruction handling in a self-timed marking system |
摘要 |
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.
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申请公布号 |
US5931944(A) |
申请公布日期 |
1999.08.03 |
申请号 |
US19970996756 |
申请日期 |
1997.12.23 |
申请人 |
INTEL CORPORATION |
发明人 |
GINOSAR, RAN;KOL, RAKEFET;STEVENS, KENNETH SCOTT;BEEREL, PETER A.;YUN, KENNETH YI;MYERS, CHRISTOPHER JOHN;ROTEM, SHAI |
分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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