| 摘要 |
PROBLEM TO BE SOLVED: To execute analysis in a short time by simulating a verification circuit before delay analysis and storing the state values of respective logic cells in a database. SOLUTION: A test pattern 1 is inputted to a circuit model 2 to analyze delay and a simulation 3 is performed. A flip-flop(F/F) to be operated at the clock edge of a clock pattern, the logic cell name of a combination circuit to change a signal value, high impedance after the change and unspecified logic value are outputted for each clock pattern and stored in a simulation database. The input of the circuit model at the start point of observation or output terminal name of the F/F and the input terminal of the F/F at the end point of observation and the output terminal name of the circuit model are inputted 5. All signal lines and logic cells related to the start and end points of observation are extracted from signal lines in the circuit model 2 by signal route retrieval 6, the pattern value of the test pattern used at the time of simulation 3 is inputted 7 to these data, and the logic cell and signal line to be operated in this pattern are extracted.
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