Integrated memory with segmented word line

摘要

The integrated word memory has memory cells (MC) at crossing points of word (WL) and bit (BL) lines, each with a selection transistor (T) which connects the cell to one bit line and whose control connection is connected to one word line. The word lines have several separate segments (2) of a first conductivity material in a first plane and a conducting track (1) of a higher conductivity material in a second plane. The word line conducting tracks are connected to word line driver (DRV) outputs. The word line segments are connected to corresp. word line tracks and to the control connections of the selection transistors of a different number of memory cells, which decreases along the word line conducting track away from the corresp. driver.