| 摘要 |
PROBLEM TO BE SOLVED: To speed up reset operation and reduce cycle time by enabling a sense amplifier to amplify a pair of bit lines, enabling a bit line clamper to supply a precharge level to the pair of bit lines, and equipping the first and second pair of lines with a bit line short-circuiting circuit for short-circuiting the pair of bit lines. SOLUTION: A sense amplifier driver SAD conducts electricity and a sense amplifier SA is activated. In response to a column selection signal c1, a first pair of bit lines BLO/BL is connected to a pair of data bus lines DB/DB to output a read signal. When data is rewritten into a memory cell MCO, the sense amplifier driver SAD is disabled to conduct electricity and the sense amplifier SA is deactivated. A transfer control signal blt1 and a clamper control signal brs rise, a bit line transfer BLT1 at a left side conducts electricity, the first pair of bit lines are short-circuited by a short-circuiting circuit SHO, and a clamper circuit clamps both the pair of bit lines to a precharge level Vii/2.
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