| 摘要 |
PROBLEM TO BE SOLVED: To ensure a high speed operation of a semiconductor circuit of the CMOS system even when a low voltage is employed for a power supply voltage. SOLUTION: In the case of placing a data transmission circuit including logic circuits 47-51 between flip-flop circuits 44-46 and a flip-flop 52, logic circuits that are especially designed so that an output falling speed is higher than an output rising speed are employed for logic circuits 47, 50 whose output may descend from an H level to an L level at data transmission, and logic circuits that are especially designed so that an output rising speed is higher than an output falling speed are employed for logic circuits 48, 49, 51 whose output may rise from an L level to an H level at data transmission.
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