| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of address bus lines and to enhance degree of integration by buffering a first address signal, delaying the buffered address signal for a prescribed time, buffering the buffered address signal and the delayed address signal and generating a second address signal. SOLUTION: When a read-out command is outputted, and an external address buffer 41 receives the address signal, a read-out control signal CASATV6-RD becomes high, and an NMOS transistor G18 is turned on. A write-in control signal CASATV6-WT and a burst control signal ICASATV6 become low, and the NMOS transistors G50, G19 are turned off. When a delay element 43 causes the buffered address signal to delay by two clocks by through a write-in command, the write-in control signal CASATV6-WT becomes high, and the NMOS transistor G50 is turned on.
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