Dual-mode memory devices and methods for operating same

摘要

A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.

主权项

1. A memory comprising:
a semiconductor strip including a channel region, a p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent a second side of the channel region; a plurality of word lines arranged to cross the semiconductor strip at cross points in the channel region; a bit line coupled to a first end of the semiconductor strip and a reference line coupled to a second end of the semiconductor strip; charge storage structures disposed between word lines in the plurality of word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip; and circuitry coupled to the plurality of word lines, to the bit line and to the reference line, configured to execute read, program and erase operations for selected memory cells on the semiconductor strip, the operations including at least one operation in which unselected word lines on both sides of a selected word line are negatively biased, and at least one other operation in which unselected word lines on both sides of a selected word line are positively biased, wherein the circuitry is configured to execute an erase operation for a single selected cell in a selected semiconductor strip including applying negative bias voltages to word lines of unselected cells to induce p-type carriers in the semiconductor strip, and a program operation for a single selected cell in a selected semiconductor strip including applying positive bias voltages to word lines of unselected cells to induce n-type carriers in the semiconductor strip.