| 摘要 |
PROBLEM TO BE SOLVED: To observe the state of a bus even without providing the bus with a bus monitor. SOLUTION: A CPU 10 observes states in which a RAM 14 and 1st and 2nd ROMs 16 and 18 are accessed with a bus monitor 34 provided in a memory controller 12 through a CPU bus 20 and the controller 12. Information obtained with this observation is stored in a sequential trace memory 38 for each bus cycle. In the case abnormality occurs in a page printer, etc., the state of the CPU bus can be known by fetching and analyzing the information stored in the memory 38, and an abnormality cause can be traced in its turn.
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