发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To reduce costs by reducing chip sizes of a synchronous DRAM or the like by reducing an amount of hardware of circuits necessary for bank control of the synchronous DRAM or the like having a plurality of banks. SOLUTION: In a synchronous DRAM having, for example, eight banks capable of executing independently each of the selection operation of a word line and the amplifying operation of a read-out signal, by providing to all banks in common a bank selection circuit BS to turn bank selection signals BA0-BA7 selectively into an effective level and a row control circuit RC generating sense amplifier drive control signals SAE1-SAE2 necessary for amplifying operation of a bank pre-charge control signal PRE and the read-out signal, as well as providing a bank control circuit BC0 or the like including each flip-flops selectively switching to a set state or a reset state following the bank selection signals and control signals, and based on the flip-flop state and the above described control signal, a specified bank is selectively activated or de-activated.
申请公布号 JP2000331475(A) 申请公布日期 2000.11.30
申请号 JP19990140458 申请日期 1999.05.20
申请人 HITACHI LTD 发明人 MATSUMOTO YOSHINORI;OOISHI TSURATOKI
分类号 G11C11/401;G11C11/407;(IPC1-7):G11C11/401 主分类号 G11C11/401
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