| 摘要 |
PROBLEM TO BE SOLVED: To shorten the time needed for processing in a pipeline cycle and to shorten the total instruction execution time by dividing a 1st instruction read-in stage of conventional 5-stage pipeline constitution into two parts for the update of a program counter and the reading of an instruction memory. SOLUTION: The 1st stage which requires the longest time for processing in 5-stage pipeline constitution is divided into two stages for updating the program counter PC and accessing an instruction memory IMEM. At a 3rd stage, a register fetch processing for fetching values from an instruction decoder DC and a general register is performed and at a 4th stage, arithmetic logical operation, data address calculation, or branch calculation of the effective address of a branch destination is performed. At a 5th stage, a memory access processing to a data memory DMEM or branching processing is performed at a 6th stage, an arithmetic processing or a writing processing to the general register is performed. Then 6-stage pipeline constitution is obtained as the whole.
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