| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the delay of the operation timing of a DQ buffer can be prevented without suppressing activation of a DQ buffer selecting signal by a R/D hit signal and the operation speed can be increased. SOLUTION: The semiconductor memory has a spare memory cell for relieving a defect and a redundancy circuit for replacing a memory cell in which a defect has occurred is replaced by a spare memory cell in which DQ buffer 34A and 34B used for write and read of data are different respectively in a normal mode and a redundancy mode in the same cycle. The device is characterized in that a R/D hit signal SRDHIT disabling the DQ buffer 34A of a normal side is masked and a DQ buffer active signal SDQBAC is activated according to the decision of the R/D hit signal at the time of a redundancy mode. Thereby, operation speed of the DG buffer on the normal side can be increased.
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