发明名称 RECONFIGURABLE FRACTIONAL-N FREQUENCY GENERATION FOR A PHASE-LOCKED LOOP
摘要 In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.
申请公布号 US2016322979(A1) 申请公布日期 2016.11.03
申请号 US201514700695 申请日期 2015.04.30
申请人 Xilinx, Inc. 发明人 Upadhyaya Parag;Bekele Adebabay M.;Turker Melek Didem Z.;Wu Zhaoyin D.
分类号 H03L7/095;H04B1/50;H03M3/00 主分类号 H03L7/095
代理机构 代理人
主权项 1. A phase-locked loop (PLL) circuit, comprising: an error detector operable to generate an error signal in response to comparison of a reference signal having a reference frequency and a feedback signal having a feedback frequency; an oscillator, coupled to the error detector, operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times the reference frequency; a frequency divider, coupled to the oscillator, operable to divide the output frequency of the output signal to generate the feedback signal based on a divider control signal; a sigma-delta modulator (SDM), coupled to the frequency divider, operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM including a plurality of stages that are selectively enabled responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM through the order select signal.
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