| 摘要 |
PURPOSE: A binary adder selecting a carry is provided to enhance a calculating velocity by selecting with respect to a carry transmission from the least significant bit to the most significant bit rapidly. CONSTITUTION: A PK generator(10) comprises eight blocks(BYTE0¯BYTE7), and each block receives an addend(A) and a summand(B) by 8-bit. The PK generator(10) generates propagation signals(P(63:0)) and kill signals(K(63:0)). A manchester carry chain(20) receives the propagation signals(P) and kill signals(K) and generates a group transmission signal(P70(7:0)), a partial deletion signal(K74(7:0)) and a group deletion signal(K70(7:0)). A local carry chain(30) receives the propagation signals(P) and kill signals(K) from the PK generator(10) and outputs a carry output signal(C0(63:0)) as a carry signal of the lower bit is '0' and outputs a carry output signal(C1(63:0)) as a carry signal of the lower bit is '1'. A byte carry generator(40) receives the group transmission signal(P70(7:0)), a partial deletion signal(K74(7:0)) and a group deletion signal(K70(7:0)) from the manchester carry chain(20) and generates a carry selection signal(CIN_BYTE(7:0)) displaying whether the carries created in each block is transmitted to the upper block. A carry selecting and adding circuit(50) responses to the carry selection signal(CIN_BYTE(7:0)) and selects one signal out of carry signals(C0,C1) inputted from the local carry chain(30). The carry selecting and adding circuit(50) outputs an added signal(S(63:0)) by performing exclusively OR of a transmission signal inputted from the PK generator(10).
|
