发明名称 RADIAL ARM MEMORY BUS FOR HIGH-AVAILABILITY COMPUTER SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a high-availability function and an improved disconnection together with a memory configuration for minimizing the capacitive load of board trace while suppressing the influence of capacitive load by a memory device at a minimum. SOLUTION: This memory is configured with a memory controller, a signal central switch, a data bus electrically coupled to the memory controller and the central switch and plural N memory modules. In this case, each of plural N memory modules is radially connected to the central switch by a correspondent memory modules bus. The central switch is physically located on a memory board and made effective for providing a point-to-point bus between the memory controller and a memory device on the memory module in the combination with the parallel connection of the memory module. For use with a high- availability fault allowance system, the memory modules are units exchangeable on the job site and are electrically disconnected.
申请公布号 JP2001167045(A) 申请公布日期 2001.06.22
申请号 JP20000328149 申请日期 2000.10.27
申请人 HEWLETT PACKARD CO <HP> 发明人 MICHAEL B REINHAMU;HANS A WIGGERS
分类号 G06F13/16;G06F13/40;G06F13/42;(IPC1-7):G06F13/16 主分类号 G06F13/16
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