Phase locked loop with a frequency multiplier and method of configuring the phase locked loop

摘要

A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.

主权项

1. A phase locked loop (PLL) circuit, comprising:
a frequency multiplier comprising a first clock input and a first clock output; and a fractional-N type PLL comprising a second clock input and a second clock output, wherein
the first clock output of the frequency multiplier is electrically connected to the second clock input of the fractional-N type PLL;a loop bandwidth of the frequency multiplier is less than a loop bandwidth of the fractional-N type PLL; andat least one of the frequency multiplier or the fractional-N type PLL comprises a configurable pin, and the at least one of the frequency multiplier or the fractional-N type PLL is configured to adjust the corresponding loop bandwidth in response to a logic value at the configurable pin.