| 摘要 |
Redundant cell arrays 201 of a plurality of columns are provided for replacing a defective bit line of a memory cell array 101. Each of the redundant cell arrays 201 is provided with a redundant sense amplifier circuit 105 separately from a sense amplifier circuit 103 of the memory cell array 101. A defective address storing circuit 108 stores a defective address of the memory cell array 101, an input/output terminal, to and from which data corresponding to the defective address are. to be inputted and outputted, and a column set number of the redundant cell array which is to be replaced in accordance with the input/output terminal. An address comparator circuit 109 detects the coincidence of an input address with the defective address. A switch circuit 112 is controlled by the coincidence detection output to switch one corresponding to the defective address of a sense amplifier circuit to one selected by the set number in the redundant sense amplifier circuit, to connect it to a data input/output buffer 113. Thus, it is possible to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions of the cell array.
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