Offset and decision feedback equalization calibration

摘要

A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

主权项

1. A receiver circuit, comprising:
a first sampling circuit configured to sample during a first calibration period, a first repeating bit position within a first signal pattern based on a first equalization parameter, the first repeating bit position having varying values over multiple transmission periods in the first signal pattern according to a known data pattern, the first signal pattern having a second repeating bit position of fixed latency relative to the first repeating bit position, the second repeating bit position in the first signal pattern having a first fixed logic value; and an error comparator circuit configured to vary the first equalization parameter during the first calibration period while the first sampling circuit samples the first repeating bit position, to compare first resultant digital samples of the first repeating bit position with the known data pattern, and to set the first equalization parameter of the first sampling circuit in response to the comparing.