| 摘要 |
PURPOSE: An input/output interfacing circuit is provided to prevent the delay of movement and reduce an error generation by dividing respectively an address bus using the control bus and by reducing a number of an address decoder line. CONSTITUTION: A first connector(86) outputs data inputted from a sensor and data indicating an operating status through an external bus. A second connector(88) is connected with a CPU(Central Processing Unit) through the external bus. A decoder outputs an enable signal for enabling a buffer and a reset signal(RET) for resetting the buffer by decoding a control signal provided from the CPU through the second connector(88). First to fourth external signal input units divide a power source so as not to influence the input data as data is inputted from all sorts of sensors through the first connector(86), and transfer the input data. First to fifth buffers perform a buffering on the external input data from the first to fourth external signal input unit, in response to the enable signal from the decoder, and output the data buffered to the CPU through the second connector(88). First to third output signal input units(58,60,62) divide a power source so as not to influence the output data as the output data is inputted from the CPU through the second connector(88), and transfer the output data to sixth to eighth buffers(46,48,50). First to third drivers(70,72,74) receive the external output data from sixth to eighth buffers(46,48,50) and output it trough the first connector(86).
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