Method for implementing wide gates and tristate buffers using FPGA carry logic

摘要

A method for implementing wide gates and tristate buses using FPGA carry logic. Wide gate logic functions and tristate buses are detected and implemented with a plurality of LUTs and carry multiplexers. The wide gate functions are of the form:where $ represents a logic operator such as AND, OR or XOR.Thus the method includes the commonly used functions FAND=i1 AND i2 AND i3 AND . . . in; and FOR=i1 OR i2 OR i3 . . . in.as well as many mixed functions. The LUTs implement the respective portions of functions f0 through fm and the carry multiplexers implement the logic operators that connect the functions in a cascaded manner. A tristate bus definition includes a plurality of bus input signals and a plurality of bus select signals, each of the bus input signals associated with one or more of the bus select signals. The tristate bus is implemented by applying input and enable signals of the tristate bus to LUT input terminals, implementing inverted sum-of products of the input and enable signals and applying the output signals to the carry chain.