| 摘要 |
<p>The integrated electronic device (10) with reduced internal connections comprises a first memory device (11), having signal pins (11a, 11d), data pins (11b1), and an enabling pin (11c) receiving a first enabling signal (CE1), and a second memory device (12) having signal pins (12a, 12d), data pins (12b1), and an enabling terminal (12c) receiving a second enabling signal (CE2). The signal pins (12a, 12d) of the second memory device (12) are connected directly to corresponding data pins (11b1) of the first memory device (11). In addition, the first memory device (11) comprises first connecting means (19), which can be activated selectively in order to define a current path between each signal pin (11a, 11d) and each data pin (11b1), and the second memory device (12) comprises second connecting means (22), which can be activated selectively in order to define a current path between each signal pin (12a, 12d) and each data pin (12b1). <IMAGE></p> |
