| 摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit wherein delay of a clock signal can be restrained and operation is stable, and a method for manufacturing the integrated circuit. SOLUTION: A logic circuit 2 like a flip-flop which adjusts operation timing by using an inputted clock signal is arranged on a substrate 6. A clock line 3 for supplying the clock signal to the logic circuit 2 is formed so as to constitute annular clock main lines 3a, etc., on the substrate 6.
|
