Semiconductor memory device with redundancy logic cell and repair method

摘要

A semiconductor memory device includes an address buffer for receiving an external address. A row decoder and a column decoder respectively decode a row address and a column address, and respectively generate a word line selecting signal and a bit line selecting signal. A memory cell array has cells. Each cell is activated by a selection of a word line and a bit line. A redundancy logic cell replaces defect cells in the memory cell array. Latches store defect cell addresses corresponding to the defect cells in the memory cell array. Comparators output repair signals when an address stored in the latches corresponds to the external address. A redundancy controller generates a control signal to intercept signals corresponding to the defect cells in response to a repair signal, and generates another control signal to enable a read/write operation of the redundancy logic cell in place of the defect cells.