发明名称 Application of wire bonding technology on wafer bump, wafer level chip scale package structure and the method of manufacturing the same
摘要 A wire bonding technique applied to wafer bump and wafer level chip size package structure and the method of manufacturing thereof comprising under no repassivation layer and without an under bump metallurgy layer, direct forming metal bump on a metal pad of a wafer surface, ball bump, method being employed to form metal bump, and wire bonding of ultrasonic vibration being used to join a suitable metal wire on the metal pad, next pulling off the metal wire and leaving the metal bump, the height of the metal bump is controlled by the parameters of the type, diameter and wire bonding of the metal wire; planarizing the metal bump of all wire bonding to an appropriate height using metallurgical tools; implanting solder bump by means of implant ball or solder printing technology on the metal bump, and an under bump metallurgy layer being formed on the top face of the metal block by means of metal deposition method in case an unfavorable intermetallic compound is formed between the metal (used for the metal bump) and the solder ball, and then proceeded to implantation.
申请公布号 US2002056741(A1) 申请公布日期 2002.05.16
申请号 US20010834629 申请日期 2001.04.16
申请人 SHIEH WEN LO;FU-YU HUANG;CHANG TU FENG;CHUANG YUNG-CHENG 发明人 SHIEH WEN LO;FU-YU HUANG;CHANG TU FENG;CHUANG YUNG-CHENG
分类号 B23K20/00;H01L21/60;H01L23/485;(IPC1-7):B23K1/06;B23K5/20;B21D39/00 主分类号 B23K20/00
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