发明名称 DEFECT ANALYZING METHOD IN SEMICONDUCTOR PRODUCT MANUFACTURING PROCESS
摘要 PROBLEM TO BE SOLVED: To provide a defect analyzing method in a semiconductor product manufacturing process in which intrinsic defects are detected on the basis of transfer of defects generated in each process to the following processes, and analysis of yield information corresponding to a process and prediction of yield in the course of a process are enabled. SOLUTION: The intrinsic defects turning to a cause of imperfect operation are detected and counted to plural function blocks formed in plural chips on a wafer. With respect to the counted intrinsic defects, failure judgment is performed to a function element of the function block in such a manner that Block 0 to Block 2 set a count value 1 as failure judgment reference and Block 3 to Block 6 set a count value 10 as failure judgment reference. On the basis of the judged result, the ratio of the number of imperfect chips to the total number of chips of a wafer is calculated as a killer rate. Final prediction of yield on the basis of relationship between yield of a production line and the killer rate, adjustment of the final prediction yield by the control of the killer rate, and improvement of the final prediction yield by level control of the killer rate in the course of a process are enabled.
申请公布号 JP2002151561(A) 申请公布日期 2002.05.24
申请号 JP20000347009 申请日期 2000.11.14
申请人 SONY CORP 发明人 TANAKA TORU
分类号 H01L21/66;H01L21/02;(IPC1-7):H01L21/66 主分类号 H01L21/66
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