发明名称 |
Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same |
摘要 |
An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.
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申请公布号 |
US6490223(B1) |
申请公布日期 |
2002.12.03 |
申请号 |
US20000614783 |
申请日期 |
2000.07.12 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
HAN SANG-JIB;KIM DU-EUNG;KWAK CHOONG-KEUN;SHIN YUN-SEUNG |
分类号 |
G01R31/26;G01R31/28;G01R31/30;G01R31/3185;G11C29/00;G11C29/06;G11C29/50;H01L21/66;(IPC1-7):G11C8/00 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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