发明名称 Delay time calculating method for use in hierarchical design
摘要 There is provided a delay time calculating method for use in a hierarchical design, capable of accurately calculating the delay amount at a boundary between different level layers in a hierarchical structure. A whole chain (T$01 to T$13) is divided into a first partial chain (T$04 to T$10) and a second partial chain (T$01 to T$03, T$11 to T$13). A first delay amount (TD(4-10)) of the first partial chain (T$04 to T$10) is calculated. A third partial chain (T$01 to T$05, T$09 to T$13) consisting of the second partial chain (T$01 to T$03, T$11 to T$13) and a plurality of chain elements (T$04 to T$05, T$09 to T$10) included in an end region of the first partial chain (T$04 to T$10), is generated, and a second delay amount (TD(1-5), TD(9-13)) of the third partial chain (T$01 to T$05, T$09 to T$13) is calculated. An end chain element (T$05, T$09) of the above mentioned plurality of chain elements (T$04 to T$05, T$09 to T$10) is separated from the third partial chain (T$01 to T$05, T$09 to T$13), and a third delay amount (D(5), D(9)) of the end chain element (T$05, T$09) is calculated. The third delay amount (D(5), D(9)) is subtracted from the second delay amount (TD(1-5), TD(9-13)) to obtain a fourth delay amount (TD(1-4), TD(10-13)). The fourth delay amount (TD(1-4), TD(10-13)) is overwritten to the first delay amount (TD(4-10)) in units of chain elements to calculat
申请公布号 US6493660(B2) 申请公布日期 2002.12.10
申请号 US20010828778 申请日期 2001.04.10
申请人 NEC CORPORATION 发明人 SAITO WATARU
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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