| 摘要 |
A mode control circuit for a semiconductor device and a semiconductor memory device having the same include a mode entrance portion for outputting an output signal in response to an external control signal, a mode entrance control portion for generating a mode entrance enable signal for controlling entry by the semiconductor device into a specific mode, for example a test mode, and a logic portion for logically combining the output signal of the mode entrance portion and the mode entrance enable signal to generate a mode signal for setting the specific mode. The mode entrance control portion includes a first fusing portion including a first fuse, a second fusing portion including a second fuse, and a mode entrance control signal generating portion for activating the mode entrance enable signal in a case where the first and second fuses are maintained at an initial state or are changed at the initial state, and deactivating the mode entrance enable signal in a case where only one of the first and second fuses is changed at the initial state. The mode control circuit prevents the occurrence of errors if the semiconductor device were to improperly enter the specific mode in an end-use system in which the semiconductor device is installed.
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