| 摘要 |
Cache-coherence computer systems represent cache-lines associated with their processors by linked and shared lists, which can be read-only or read-write. In read-only lists all cache-line copies are the same and may be read by multiple processors at the same time, while read-write lists allow only the head of the list to write to its cache and to invalidate stale cache entries after writing. Main memory of the system always points to the head of the list and includes indications of memory-line states for fresh, stale or no cache line exists. A memory line becomes stale when its associated cache line is modified. A read-write processor seeking to update a cache line requires updating the list from read-only to read-write. A copy of the tail entry is created and made the head of the list, resulting in one entry being in two places on the list. The cache is then updated and invalidation starts concurrently in both directions from head-to-tail and from tail-to-head. Having concurrent fast forward and backward invalidations improves the overall invalidation time about four times over a slow forward invalidation alone.
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