| 摘要 |
A digital phase comparator circuit that determines and adjusts the relative phase of two digital clock signals derived from the same digital clock. The circuit having two inputs, one connected to receive each of the clock signals to be compared and including a latch circuit to receive one clock signal at the clock input, and the other clock signal at a data input. The latch circuit is arranged so that the output is equal to the signal at the data input when measured at the clock edge. The output is therefore a logic "1" when the second clock leads the first clock, and a logic "0" when the second clock lags the first clock.
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