发明名称 |
Flip-flop with advantageous timing |
摘要 |
A flip-flop includes an input stage to receive a data signal and an output stage to provide an output signal. A clock input is directly connected to a transmission gate of the output stage and coupled by way of a delay circuit to a transmission gate of the input stage. A first latch is coupled between the transmission gate of the input stage and the output stage.
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申请公布号 |
US2002190771(A1) |
申请公布日期 |
2002.12.19 |
申请号 |
US20010017303 |
申请日期 |
2001.12.13 |
申请人 |
TRANSLOGIC TECHNOLOGY, INC. |
发明人 |
TRAN DZUNG JOSEPH;ACUFF MARK WARREN |
分类号 |
H03K3/356;H03K3/3562;(IPC1-7):H03K19/00 |
主分类号 |
H03K3/356 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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