| 摘要 |
A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.
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