| 摘要 |
Briefly, in one example of the present invention, a code generator automatically produces Viterbi algorithm code for the architecture of a general-purpose processor. Upon input of version parameters such as, but not limited to, the generator polynomials, the constraint length and the rate, the code generator produces versions of Viterbi algorithm code for use in the processor. In another example, a code generator produces a description of a Viterbi accelerator. The processor may be a digital signal processor.
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