| 摘要 |
A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.
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