Semiconductor memory device

摘要

A semiconductor memory device of which the data output circuit scale is reduced and the data read speed is improved. An output control signal generation portion receives first and second output data determination signals from a sense amplifier and a level shift enable signal. The first and second output data determination signals have complementary logical levels, a maximum internal voltage, and a minimum ground voltage. The maximum voltage of the level shift enable signal is an external voltage and the minimum voltage is the ground voltage. An output portion connected with the output control signal generation portion through respective nodes outputs an output signal from another node. The maximum voltage of the output signal is the external voltage and a minimum voltage is the ground voltage.