| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which high speed operation and reduction of chip area can be achieved simultaneously. SOLUTION: This device is constituted of a block decoder/auxiliary gate decoder, a sub-decoder, a gate decoder, a selection MOS transistor, a sense amplifier, a memory cell sub-array, or the like. Memory cells C000-C030 has structure of an associative ground type sharing mutually a local drain line and a local source line being adjacent on the same word line, as they have an auxiliary gate in addition to a control gate and a floating date, an operation current is suppressed though operation is write operation by injection of hot electrons, parallel operation being equal to write operation by FN tunnel can be realized, further, as a sub-decoder 20 driving word lines comprises two NMOS for one word line, layout of a sub-decoder can be adapted to making microfabrication.</p> |
