| 摘要 |
PURPOSE: A redundancy decoder circuit is provided to reduce the power consumption by preventing unnecessary address signals applied to the unused redundancy decoder circuits. CONSTITUTION: A redundancy enable circuit(120) is used for storing the information about an operating state of a redundancy memory cell at a corresponding decoder instead of a defect memory cell. The redundancy enable circuit(120) is formed with fuses(200,202), a PMOS transistor(204) which is turned on/off according to the logic state of a control signal(CSRXYb) which is a chip selection redundancy signal interworked with a chip selection signal, NMOS transistors(206,208), an inverter(210). A precharge circuit(140) includes three PMOS transistors(212,214,216), an NMOS transistor(218) , and a NAND gate(252). The precharge circuit(140) is used for charging a precharge node of an address storage circuit(160) to a high level of a supply voltage. The address storage circuit(160) is formed with a plurality of fuses(220-230), a plurality of NMOS transistors(232-242), and a plurality of inversion elements(244-248).
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