| 摘要 |
PROBLEM TO BE SOLVED: To inactively read a cache line even if it has a large cache line size, by restricting the divided number of memory to a minimum in a set associative type cache memory. SOLUTION: The cache memory has plural ways 21, 22, 31 and 32. When a cache-hit occurs, a cache control circuit 1, expecting successive access, considers succeeding addresses from the plural ways via comparators 51 and 52, and selects data from the way at a corresponding address side. The cache memory is divided into bank memories as storing/reading divisions. Preceding bank memories 311 and 321 have smaller sizes, and succeeding bank memories 312 and 322 have larger sizes, each including latch circuit for latching memory information of the succeeding bank memory. The cache control circuit 1 is adapted to read out the information in the latch circuit of the succeeding bank memory when reading for successive addresses does not change the way. COPYRIGHT: (C)2003,JPO
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