发明名称 Transistor with improved source/drain extension dopant concentration
摘要 A method (40) of forming an integrated circuit (60) device comprising a substrate (64). The method comprises the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack comprising a gate having sidewalls. The method further comprises the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further comprises the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer comprises depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C. The method further comprises the step of fourth (50), implanting deep source/drain regions (761, 762) into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers.
申请公布号 US2003109105(A1) 申请公布日期 2003.06.12
申请号 US20020287979 申请日期 2002.11.05
申请人 MEHROTRA MANOJ;BU HAOWEN;JAIN AMITABH 发明人 MEHROTRA MANOJ;BU HAOWEN;JAIN AMITABH
分类号 H01L21/336;(IPC1-7):H01L21/823 主分类号 H01L21/336
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